Advances in semiconductor manufacturing technologies have resulted in dramatically increased circuit packing densities and higher speeds of operation. In order to achieve such increased densities, a wide variety of evolutionary changes have taken place with respect to semiconductor processing techniques and semiconductor device structures over the years.
Many of these process and structural changes have been introduced in connection with device scaling, in which ever smaller device geometries have been achieved. One consequence of conventional FET device scaling is a requirement to reduce operating voltages. The reduced operating voltages are required, at least in part, because conventional FET device scaling needs a thinner gate dielectric layer in order to produce the desired electrical characteristics in the scaled-down transistor. Without a reduction in operating voltage, the electric field impressed across the thinner gate dielectric during circuit operation can be high enough for dielectric breakdown to become a problem.
Historically, FETs have been fabricated as planar devices. FIG. 1 shows a cross-section of an exemplary, conventional, planar, FET. But a vertically oriented device, referred to as a “finFET,” has more recently been introduced into commercial semiconductor products. FIG. 2 illustrates the general arrangement of a conventional finFET.
FIG. 1 is a cross-sectional representation of a conventional planar FET. A gate dielectric layer 110 is disposed on the surface of a substrate 102. A gate electrode 108 is disposed on gate dielectric layer 110. Sidewall spacers 106 are disposed adjacent gate electrode 108 and gate dielectric layer 110. A first source/drain terminal 104, and a second source/drain terminal 112 are formed in substrate 102. First source/drain terminal 104 has a first source/drain extension 105, and second source/drain terminal 112 has a second source/drain extension 111. First and second source/drain terminals 104, 112 are symmetric with respect to gate 108.
FIG. 2 is an isometric view of an example of a conventional finFET. Substrate 202 has dielectric isolations areas 208 formed thereon adjacent to fin 204. A gate dielectric layer 214 and a gate electrode 212 together make up the conventional finFET gate structure. The gate structure “wraps” around the vertical and top sides of the fin. The source/drain terminals are those regions of fin 204 on either side of the gate electrode 212. In the conventional finFET, both source/drain terminals are adjacent to, and equidistant from gate electrode 212.
It has been recognized that many integrated circuit designs require both low operating voltage FETs for their ability to operate at high speeds, and high operating voltage FETs for their ability to interface with high voltage signals provided by other electronic components. In response to this need, manufacturers have developed and provided semiconductor manufacturing processes that offer two types of transistors for use within a single integrated circuit. These two types of transistors include a first type with low operating voltage and high speed, and a second type with a higher operating voltage and a lower speed.
Unfortunately, these semiconductor manufacturing processes do not provide finFETs with the electrical characteristics of high speed and high operating voltage combined in a single device.
It is noted that the drawn representations of various semiconductor structures shown in the figures are not necessarily drawn to scale, but rather, as is the practice in this field, drawn to promote a clear understanding of the structures and process steps which they are illustrating.